The present invention relates to highly integrated circuit arrangements formed on chips for data processing devices, and particularly arrangements fabricated according to the MOS technique, and of the type including a first chip containing a central arithmetic and control unit (RSE) and at least one further chip containing memories, with the chips being connected together by means of a bus containing, inter alia, a plurality of data lines and in which the contents of one or a plurality of memories is continuously read out under control of an address register.
Various circuit arrangements on MOS chips of the above-described type are known in the art. The memory chips which contain, inter alia, the operating program of the instrument for which the circuit arrangement is intended in the form of a series of micro-instructions, are connected with the RSE via a collecting cable made up of an address bus, a data bus and a control bus. The RSE chip includes a settable address register which is switched on by counting pulses and which is able to receive an entire address of, for example, 14 bits.
Each memory location in the memory chips has an address associated therewith. Each address is conducted from the RSE via the bus to each one of the connected memory chips. There it is decoded and then one of the memory chips is selected and thereupon the appropriate memory location in the selected memory is addressed. The contents of the addressed memory location are now available for possible transfer to the RSE until the next address calls up the next-following memory location.
A special problem in the field of MOS circuitry is that the high resistance associated therewith limits the maximum operating frequency. As a result, the operational speeds are low. Thus, MOS circuit arrangements are inferior, as regards operating speed, to those designed according to the bipolar technique.
The time required for calling up a memory location by an address can, in principle, be divided into two time periods: a first time period for conducting the address from the address register of the RSE chip to the respective memory chip; and a second time period for decoding the address and addressing the memory location in the memory chip.
Additionally, as a result of the extremely small size of the chips, the number of connecting contacts on each chip is very limited. If the addresses consist of a large number of bits (for example 14 bits) a parallel transmission would require 14 address lines and thus 14 connecting contacts. Since the remaining number of connecting contacts is generally no longer sufficient to accommodate all of the other required lines, the multiple bit addresses are often subdivided. Thus fewer lines and connecting contacts are required and every address is transmitted in the form of several successive bit groups. However, this even further reduces the already low operating speed.